The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technology which is effective if applied to a semiconductor integrated circuit device composed of memory cells having a full CMIS (Complementary Metal Insulator Semiconductor) structure.
The memory cells of an SRAM (i.e., Static Random Access Memory) each storing information of 1 [bit] are arranged at intersections between word lines and complementary data lines (complementary data line pairs). A plurality of these SRAM memory cells are arranged in a matrix in the extending directions of the word lines and the complementary data lines to constitute a memory cell array.
Each memory cell of an SRAM is composed of a flip-flop circuit (or an operational amplifier) and two transfer MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The flip-flop circuit is constituted as an information storage unit comprising two drive MOSFETs and two load elements. The two transfer MOSFETs and the two drive MOSFETs are of n-channel conduction type.
The memory cell of the SRAM is exemplified by the full CMOS structure in which the load elements are made up of p-channel conduction type load MOSFETs. The memory cell of this full CMOS structure has its p-channel type load MOSFET, n-channel type drive MOSFET and n-channel type transfer MOSFET all formed in a semiconductor substrate. The memory cell of this full CMOS structure is featured by: (1) a low power consumption; (2) a high speed operation; (3) necessity for neither high resistance polysilicon nor polysilicon PMOS to be laminated over the MOSFETs, but for only the CMOS thereby to simplify the manufacturing process; (4) a stable operation even at a low voltage by the drive of the load MOSFETs; and (5) a high resistance to alpha rays. Thus, the memory cell of the full CMOS structure can be widely used in a super-high speed memory such as a large-sized computer, thanks to the aforementioned feature (2), and in a storage unit of a CMOS logic LSI or microprocessor LSI, thanks to the aforementioned feature (3).
In the memory cell having the full CMOS structure, the source region of the n-channel type drive MOSFET is connected to an operation power line fixed at the operation potential (e.g., xe2x88x922.5 [V]), and the source region of the p-channel type load MISFET is connected to a reference power line fixed at a reference potential (e.g., 0 [V]). Moreover, the drain regions of the n-channel type drive MOSFET and the p-channel type load MOSFET are connected to each other through intra-cell wirings. The power supply line, the reference potential line and the internal wirings are formed of the first level metal wiring layer. Still moreover, either the source region or the drain region of the n-channel type transfer MOSFET is connected through the intra-cell wirings with complementary data lines formed of the second level metal wiring layer.
Incidentally, the memory cell of the SRAM having the aforementioned complete CMOS structure is disclosed in Japanese Patent Application No. 294576/1992, for example.
We have found out the following problems of the aforementioned SRAM.
In this SRAM, all the power supply line, the reference potential line and the intra-cell wirings are formed of the first level metal wiring layer. Since the size of the memory cell is determined by the first level metal wiring layer, it is difficult to reduce the memory cell size even if the semiconductor elements such as the drive MOSFETs, the transfer MOSFETs and the load MOSFETs are miniaturized.
In the memory cell region, more specifically, the power supply lines and the reference potential lines individually extend in the same direction as that of the word lines, and the intra-cell wirings for connecting the drain regions of the p-channel type load MOSFET and the n-channel type drive MOSFET with each other extend between the power supply line and the reference potential line in the direction perpendicular to the word lines (i.e., in the direction in which the complementary data lines extend).
Between the power supply lines of the memory cells adjacent to each other in the extending direction of the complementary data lines, moreover, there arranged the intra-cell wirings for connecting the n-channel type transfer MOSFET and the complementary data lines.
These power supply line, reference potential line and intra-cell wirings are formed at distances no less than the minimum process size of the wirings. Thus, there arises the aforementioned problem that the size of the memory cell is enlarged.
An object of the present invention is to provide a technology capable of reducing the size of memory cells in a semiconductor integrated circuit device and having the full CMIS structure. Another object of the present invention is to provide a technology capable of achieving the aforementioned object and to enhance the degree of integration of the semiconductor integrated circuit device having the memory cells of the full CMIS structure.
The foregoing and other objects and novel features of the present invention will become apparent from the following description to be made with reference to the accompanying drawings.
A representative of the invention to be disclosed herein will be briefly described in the following.
According to the present invention, there is provided a semiconductor memory device comprising) word lines extending in a column direction, complementary data lines extending in a row direction, and memory cells having first and second inverters which are arranged at the intersections between the word lines and complementary data lines, in each of which the drain regions of a p-channel type load MISFETs and a n-channel type drive MISFET are electrically connected to each other, the gate electrodes thereof are electrically connected to each other, the source region of the p-channel type load MISFET is coupled to a first fixed potential line, and the source region of the n-channel type MISFET is coupled to a second fixed potential line, and the inputs and outputs of which are cross-coupled to each other; wherein the p-channel type load MISEFETs of a plurality of memory cells arranged in the column direction are formed in n-channel well regions in the direction in which the word lines extend, and the source regions of the p-channel type load MISFETs of the memory cells and the n-type well regions are electrically connected to each other through conductor layers, which are formed independently of the plurality of memory cells arranged in the column direction.
By the above-specified means, the well regions can be used as the power supply line to feed the reference potential (or earth potential) or the operation potential (or power supply potential) to the source region of the load MISFET of each memory cell. As a result, it is possible to eliminate the power supply line formed of the first level metal wiring layer on the memory cell and to reduce the cell size of the memory cell.
Since the cell size of the memory cell can be thus reduced, it is possible to enhance the degree of integration of the semiconductor integrated circuit device which is composed of the memory cells having the full CMIS structure.